Redundant memory channel array configuration with data striping

Details Redundant memory channel array configuration with data striping Redundant memory channel array configuration with data striping

1994-03-07

1995-10-31

Envall, Jr., Roy N.

Excavating

371 404, 395821, 39518319, 39518207, H03M 1300, G06F 1100

Patent

active

054636434

ABSTRACT:
A memory channel array configuration wherein two or more memory channels are used for data transfer and data is striped across each of the memory channels. In addition, one or more redundant memory channels, preferably a single dedicated parity channel, are used for error correction. In the preferred embodiment the memory channel configuration utilizes RAMBUS based memory channels, and thus the present invention provides error correction for a RAMBUS based memory system. Also, the use of multiple memory channels in conjunction with data striping across each of the channels allows for much higher data transfer bandwidths than is available using prior art implementations of RAMBUS technology.

REFERENCES:
patent: 4092732 (1978-05-01), Ouchi
patent: 5301297 (1994-04-01), Menon et al.
patent: 5305326 (1994-04-01), Solomon et al.
patent: 5309451 (1994-05-01), Noya et al.
patent: 5315602 (1994-05-01), Noya et al.

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