Multi-bank semiconductor memory device having common command det

Details Multi-bank semiconductor memory device having common command det Multi-bank semiconductor memory device having common command det

1994-03-18

1995-10-31

Nelms, David C.

Static information storage and retrieval

Addressing

Plural blocks or banks

365203, 365222, G11C 1140

Patent

active

054635900

ABSTRACT:
A DRAM comprises: a memory cell array divided into a plurality of banks (34, 35; 43, 46) each having a plurality of dynamic type memory cells arranged into substantially a matrix pattern, data being writable in and readable from each memory cell and further the data written in the memory cells being refreshable; activating sections (28, 30) for activating the memory cells to be read, written and refreshed; precharging sections (29, 31) for precharging data lines connected to the memory cells to be read; and command detecting circuits (1, 6, 12, 18, 23) for detecting commands and outputting control signals corresponding to the detected commands, to operate the DRAM in correspondence to the respective commands, each of a plurality of command detecting circuits (1, 6, 12, 18, 23) being provided for a plurality of the banks in common to detect one command. In a computer system having a high speed CPU, for instance, since the CPU and memory can be activated by use of a single clock, it is possible to realize a high speed memory so as to correspond to the high speed CPU, by simplifying the clock control.

REFERENCES:
patent: 4829484 (1989-05-01), Arimoto
patent: 4961167 (1990-10-01), Kumanoya
patent: 4989183 (1991-01-01), Kumanoya
patent: 5295109 (1994-03-01), Nawaki

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