Squaring circuit for binary numbers

Details Squaring circuit for binary numbers Squaring circuit for binary numbers

1995-08-01

1996-10-29

Mai, Tan V.

Boots, shoes, and leggings

364735, G06F 738, G06F 1532

Patent

active

RE0353655

ABSTRACT:
A squaring circuit for a binary number X of n bits x.sub.0 to x.sub.n-1, includes a table of the squares of numbers p constituted by bits x.sub.1 to x.sub.n-2. An adder for adding numbers of 2n-3 bits receives at a first input a number constituted by bit x.sub.n-1, positioned on the left of the square p.sup.2 provided by the table. A first switching element receives the number p and provides same to the n-2 low weight lines of a second input of the adder if bit x.sub.0 is equal to 1. A second switching element receives number p and provides same to the n-2 high weight lines of the second input if bit x.sub.n-1 is equal to 1. An AND gate is connected to the remaining line of the second input and receives the bits x.sub.0 and x.sub.n-1. The square X.sup.2 of X is constituted by the adder output, to which a bit 0 and the bit x.sub.0 are positioned on the right.

REFERENCES:
patent: 4313174 (1982-01-01), White
patent: 4410956 (1983-10-01), Yoshida
patent: 4787056 (1988-11-01), Dietrich
Computer Design, vol. 11, No. 4, Apr. 1972, Littleton, MA, pp. 100-104, A. Hemel "Square Root Extraction with Read-Only Memories".

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