Electrostatic discharge protection with hysteresis trigger circu

Details Electrostatic discharge protection with hysteresis trigger circu Electrostatic discharge protection with hysteresis trigger circu

1994-05-09

1995-10-31

Deboer, Todd

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361 91, H02H 906

Patent

active

054635209

ABSTRACT:
An integrated circuit obtains improved ESD protection by way of a shunt protection circuit having a trigger level that exhibits a hysteresis effect with respect to voltage applied to the bondpads. The hysteresis is obtained by a string of voltage dropping transistors that produce a trigger voltage level at an intermediate node, and a shorting transistor that effectively removes at least one transistor from the string. In a typical case, a PNP bipolar transistor serves as the protective device in the circuit to carry the ESD current from the bondpads. An illustrative embodiment with p-channel voltage dropping transistors and an n-channel shorting transistor is shown, along with additional capacitive boost circuitry for speeding up circuit operation. In this manner, a high peak ESD current can be carried while ensuring non-conduction of the protection circuit for normal operating voltages, and also for voltages slightly in excess of normal power supply voltages.

REFERENCES:
patent: 4855620 (1989-08-01), Duvvury et al.
patent: 5208719 (1993-05-01), Wei
patent: 5304839 (1994-04-01), Chen et al.
patent: 5335132 (1994-08-01), DeShazo, Jr.
30th Annual Proceedings Reliability Physics 1992, San Diego, Calif., Mar. 31, Apr. 1,2, 1992 "Dynamic Gate Coupling of NMOS For Efficient Output ESD Protection", Charvaka Duvvury et al, pp. 141-150.
Application Ser. #07/894405, Filing Date, Jun. 5, 1992, Allowed Mar. 31, 1994 (Juergen Pianka, Case 1).

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