Input slope timing analysis and non-linear delay table optimizat

Details Input slope timing analysis and non-linear delay table optimizat Input slope timing analysis and non-linear delay table optimizat

1997-12-12

2000-03-14

Teska, Kevin J.

39550006, G06F 1750

Patent

active

060383844

ABSTRACT:
The optimization process of the present invention replaces the successive delay table generation approach of the prior art with one that minimizes delay table size by generating only those indices sufficient to satisfy the error limits prescribed. This is accomplished by generating only portions of the delay table by reducing the maximum load/ramp point for each generated portion until such time as the error percentage limit is not exceeded. The load/ramp indices for the generated delay tables are those defined for the interpolation comparison table. These non-linearly distributed indices force a greater indexing range within the higher load/ramp regions, where relative interpolation error percentage are not as great as those within the lower regions. Within the present invention, the maximum load/ramp point of the last optimized portion becomes the minimum of the next portion, while the maximum load/ramp of the interpolation table becomes the next max point. Once all portions have been generated, the load and ramp indices for the optimized table will have been completely defined. This process ensures that only the minimum number of indices sufficient to satisfy the error percentage limit along the critical input ramp are generated.

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