Hardware multiplier processor

Details Hardware multiplier processor Hardware multiplier processor

1983-04-26

1986-05-13

Thomas, James D.

Boots, shoes, and leggings

364754, G06F 752

Patent

active

045890854

ABSTRACT:
A hardware processor is disclosed which in the described embodiment is a memory mapped multiplier processor that can operate in parallel with a 16 bit microcomputer. The multiplier processor decodes the address bus to receive specific instructions so that in one access it can write and automatically perform single or double precision multiplication involving a number written to it with or without addition or subtraction with a previously stored number. It can also, on a single read command automatically round and scale a previously stored number. The multiplier processor includes two concatenated 16 bit multiplier registers, two 16 bit concatenated 16 bit multipliers, and four 16 bit product registers connected to an internal 16 bit data bus. A high level address decoder determines when the multiplier processor is being addressed and first and second low level address decoders generate control signals. In addition, certain low order address lines are used to carry uncoded control signals. First and second control circuits coupled to the decoders generate further control signals and generate a plurality of clocking pulse trains in response to the decoded and address control signals.

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Lowenthal, Richard, "Floating Point Microprocessor Implemented as Optional Co-Processor", Computer Design, vol. 20, #3, Mar. 1981, pp. 178-182.

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