Fault tolerant, frame synchronization for multiple processor sys

Details Fault tolerant, frame synchronization for multiple processor sys Fault tolerant, frame synchronization for multiple processor sys

1984-05-31

1986-05-13

Heckler, Thomas M.

Boots, shoes, and leggings

371 9, 371 47, 371 61, G06F 104, G06F 1120

Patent

active

045890668

ABSTRACT:
The processors in a redundant, multiprocessor system are synchronized at the minor frame level with a combination of hardware and a local software supervisory routine. Each processor includes an interface synchronizer unit which receives synchronizing pulses from a selected number of the processor synchronizer units at the end of each minor frame. Sync decision logic circuits in each synchronizer determine whether the synchronizing pulses arrive within a predetermined time period or "window" (2 usecs, for example) indicating synchronization between the processors. A control, processor "Interrupt", signal is generated whenever a majority (>2) of the four (4) sync signals are received at the end of the minor frame. The local processor then initiates the supervisory software routine, which checks the status of the synchronizer for failure indications, isolates and records the faulty sync pulses and then replaces any faulty processor with another processor.

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