Processing circuit for operating on elements of a Galois field

Details Processing circuit for operating on elements of a Galois field Processing circuit for operating on elements of a Galois field

1982-03-22

1984-09-25

Malzahn, David H.

Boots, shoes, and leggings

364761, G06F 752

Patent

active

044738870

ABSTRACT:
An operating circuit operates on digital data words to form products or quotients of the quantities represented by the digital data words. The data words are considered as elements .alpha..sup.i of a Galois field GF(2.sup.m) where each element is a power .alpha..sup.i of an irreducible root. The data words are input into a conversion ROM which in response provides the corresponding exponents i as an output. These exponents i, j are additively combined to form a sum (i+j) or difference (i-j), and this is applied to a reverse conversion ROM. The latter then provides, as an output data word, an element .alpha..sup.i+j or .alpha..sup.i-j which is the product or quotient, respectively, of the input data words. A provision can be incorporated to compensate for division by a zero element. This circuit finds favorable application in error correction of a transmitted or recorded digital signal.

REFERENCES:
patent: 3805037 (1974-04-01), Ellison
patent: 4037093 (1977-07-01), Gregg et al.
patent: 4251875 (1981-02-01), Marrer et al.
Brubaker et al. "Multiplication Using Logarithms Implemented With ROM" IEEE Trans. on Computers, vol. C-24, No. 8, Aug. 1975, pp. 761-765.
Mitchell "Computer Multiplication & Division Using Binary Logarithms" IRE Trans. on Computers, Aug. 1962, pp. 512-519.
Laws, Jr. et al. "A Cellular-Array Multiplier for GE(2.sup.m)" IEEE Trans. on Computers, vol. C-20, No. 12, Dec. 1971, pp. 1573-1578.

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