Planar famos transistor with trench isolation

Details Planar famos transistor with trench isolation Planar famos transistor with trench isolation

1989-02-17

1990-02-27

Carroll, J.

357 2311, 357 45, 357 49, 357 54, 357 55, H01L 2978, H01L 2710, H01L 2712, H01L 2934

Patent

active

049050621

ABSTRACT:
A sealed gate FAMOS transistor (28) disposes a thermal oxide layer (40) about the floating gate (34) in order to isolate the floating gate (34) from the planar isolating regions (44) between floating gates (34). Trench isolating regions (54) are provided between control gates (50) to enhance programmability of the sealed gate FAMOS transistor (28).

REFERENCES:
patent: 4409723 (1983-10-01), Harari
patent: 4597060 (1986-06-01), Mitchell et al.
patent: 4698900 (1987-10-01), Esquivel
patent: 4713142 (1987-12-01), Mitchell et al.
patent: 4729006 (1988-03-01), Dally et al.
patent: 4763177 (1988-08-01), Paterson
Sekiya et al., "Trench Self-Aligned EPROM Technology", 1986 VLSI Symposium.

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