Fishing – trapping – and vermin destroying
Patent
1994-04-11
1995-10-31
Breneman, R. Bruce
Fishing, trapping, and vermin destroying
437 84, 437 86, 437131, H01L 21265
Patent
active
054628830
ABSTRACT:
A method for fabricating silicon on insulator structures having a dislocation free silicon layer. The method utilizes low temperature UHVCVD to deposit a very heavily doped etch stop layer having a very steep doping profile onto a substrate and a lightly doped active layer onto the etch stop layer. An insulator is formed on the active layer and a carrier wafer is formed on the insulator layer. The original substrate is removed in a first etch and the etch stop layer is removed in a second etch resulting in a thin, uniform active layer. In one embodiment, a small percentage of germanium is added to the etch stop layer to produce a defect free epitaxial active layer.
REFERENCES:
patent: 3293087 (1966-12-01), Porter
patent: 3455748 (1969-07-01), Lindmayer et al.
patent: 4000020 (1976-12-01), Gartman
patent: 4351856 (1982-09-01), Matsui et al.
patent: 4534804 (1985-08-01), Cade
patent: 4601779 (1986-07-01), Abernathey et al.
patent: 4861393 (1989-08-01), Bean et al.
patent: 5013681 (1991-05-01), Godbey et al.
patent: 5261999 (1993-11-01), Pinker et al.
Palik et al "Ellipsometric study of the Etch-stop mechanism in Heavily Doped silicon" Jr. Electrochem. Soc 132 (1985), 135-141.
Maszara, W. P., et al., "Bonding on silicon wafers for silicon-on-insulator" J. Appl. Phys. 64(10), 15 Nov. 1988, pp. 4943-4946.
Herzog, H. J., et al., "X-Ray Investigation of Boron- and Germanium-Doped Silicon Epitaxial Layers", J. Electrochem. Soc.: Solid-State Science and Technology, Dec. 1984, pp. 2969-2974.
Hirayama, Hiroyuki, et al., "Stress reduction and doping efficiency and B- and Ge-doped silicon molecular beam epitaxy films.", Appl. Phys. Lett. 52(16), 18 Apr. 1988, pp. 1335-1337.
Sze, S. M., VLSI Technology, pp. 85-89 (2d ed. 1988).
Meyerson, B. S., et al., "Nonequilibrium Boron Doping Effects in Low-Temperature Epitaxial Silicon Films", Appl. Phys. Lett., 50(2):113 (1987).
Lasky, J. B., et al., "Silicon-On-Insulator (SOI) By Bonding and Etch-Back", IEDM Technical Digest, 684 (1985).
Dennard Robert H.
Meyerson Bernard S.
Rosenberg Robert
Breneman R. Bruce
International Business Machines - Corporation
Paladugu Ramamohan Rao
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