CRC/EDC checker system

Details CRC/EDC checker system CRC/EDC checker system

1994-09-16

1997-01-07

Envall, Jr., Roy N.

Excavating

371 404, G11C 2900

Patent

active

055924980

ABSTRACT:
EDC/CRC checker (70) performs an EDC/CRC check as a block of data is being corrected during a correction pass, thereby obviating buffer access for EDC/CRC purposes subsequent to block correction. During the correction pass, an EDC/CRC sum is accumulated which, upon completion of the pass of the block, is zero if EDC/CRC bytes in the block confirm that the block has been corrected. During the single correction pass of the block, bytes of an uncorrected, most-recent codeword are added to the accumulated sum. Bytes of a previous codeword which have a byte synchronization relationship with the byte of the most-recent codeword are corrected (if necessary), and (when correction occurs) error pattern factors including error patterns used to correct the bytes of the previous codeword are also added to the accumulated sum. In the illustrated embodiment, the block is conceptualized as having columns of codewords and the byte synchronization relationship is such that when an uncorrected byte is being accumulated, correction occurs for a corresponding byte of a next previous codeword. Various embodiments of the invention are capable of handling a plurality of codewords simultaneously.

REFERENCES:
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patent: 3868632 (1975-02-01), Hong et al.
patent: 4703485 (1987-10-01), Patel
patent: 4782490 (1988-11-01), Tenegolts
patent: 5151902 (1992-09-01), Grallert
patent: 5218691 (1993-06-01), Tuma et al.
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patent: 5291584 (1994-03-01), Challa et al.
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patent: 5422895 (1995-06-01), Nguyen et al.
Patent Abstracts of Japan, vol. 13, No. 70 (P-829), 17 Feb. 1989 & JP-A-63 255876 (Matsushita) 24 Oct. 1988--see abstract.
Patent Abstracts of Japan, vol. 13, No. 73 (P-830), 20 Feb. 1989 & JP-A-63 257966 (Matsushita) 25 Oct. 1988--see abstract.

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