Non-volatile analog memory cell with double polysilicon level

Details Non-volatile analog memory cell with double polysilicon level Non-volatile analog memory cell with double polysilicon level

1995-01-03

1997-01-07

Zarabian, A.

Static information storage and retrieval

Floating gate

Particular biasing

36518503, G11C 1140

Patent

active

055924182

ABSTRACT:
Non-volatile memory cell with double level of polycrystalline silicon has a source region (38), a drain region (31), a channel region (34) between said source and drain regions, a floating gate (33), and a control gate (32) in which the channel region area extends into two lateral zones beneath the two gates and perpendicular to the source-drain direction.

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patent: 5264734 (1993-11-01), Holler et al.
R. R. Troutman, Staggered Channel EPROM/EAROM, IBM Technical Disclosure Bulletin, vol. 23, No. 4, Sep., 1980, pp. 1375-1376.
Chi-Kai Sin, et al., EEPROM as an Analog Storage Device, with Particular Applications in Neural Networks, IEEE Transactions on Electron Devices, vol. 39, No. 6, Jun., 1992, pp. 1410-1419.
A. Kramer, et al., Flash-Based Programmable Nonlinear Capacitor for Switched-Capacitor Implementations of Neural Networks, 1994, no month available.

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