Self-timed content addressable memory access mechanism with buil

Details Self-timed content addressable memory access mechanism with buil Self-timed content addressable memory access mechanism with buil

1991-07-08

1994-02-22

Sikes, William L.

Static information storage and retrieval

Associative memories

Ferroelectric cell

365194, 365210, 365233, 307269, G11C 1500

Patent

active

052894037

ABSTRACT:
A content addressable memory (CAM) access system and method having self-timing and built-in margin test features. The present invention includes a compare array which has multiple comparator paths. The comparator paths generate multiple mismatch indications after receiving a system clock signal. The present invention also includes a row driver which receives the mismatch indications produced by the compare array after receiving a Tclock signal. The row driver generates multiple row enables based on the mismatch indications. The Tclock signal is generated only after the mismatch indications are valid. Thus, the row driver always receives valid mismatch indications. According to the present invention, the Tclock signal is generated by simulating a worst case path through the compare array. The worst case path produces a dummy mismatch indication. Since the dummy mismatch indication is a product of the worst case path through the compare array, the mismatch indications must be valid when the dummy mismatch indication is valid. Thus, the dummy mismatch indication may be used as the Tclock to cause the row driver to read the mismatch indications. In other words, the dummy mismatch indication may be used as a measure of the amount of time which the compare array requires to generate valid mismatch indications.

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