Small-sized low power consumption multiplication processing devi

Details Small-sized low power consumption multiplication processing devi Small-sized low power consumption multiplication processing devi

1991-08-07

1994-02-22

Mai, Tan V.

Boots, shoes, and leggings

364760, G06F 752

Patent

active

052893987

ABSTRACT:
A multiplication processing device provided with a recoding circuit for dividing an M-digit number (M is a natural number), the radix of which is .UPSILON., into consecutive N-digit sets (N is a natural number equal to or less than M) and for calculating an intermediate sum S.sub.i and an intermediate carry C.sub.i according to Z.sub.gi =C.sub.i .times..UPSILON..sup.N +S.sub.i (Z.sub.gi is the value of an ith set (i represents natural numbers equal to or greater than a predetermined number)) and for adding the intermediate sum S.sub.i corresponding to the ith set to an intermediate carry C.sub.i-1 corresponding to an (i-1)th set for each value of i and a selection circuit for selecting one of one or more numbers having the same format as that of the intermediate carry C.sub.i corresponding to the ith set and for outputting the selected number to the recoding circuit as the intermediate carry C.sub.i-1 corresponding to the (i-1)th set.

REFERENCES:
patent: 4807175 (1989-02-01), Tokumaru et al.
patent: 4864528 (1989-09-01), Nishiyama et al.
patent: 4868777 (1989-09-01), Nishiyama et al.
patent: 5036482 (1991-07-01), Saini

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