Patent
1977-03-17
1978-10-10
Wojciechowicz, Edward J.
357 15, 357 41, 357 54, 357 59, H01L 2978
Patent
active
041199952
ABSTRACT:
An MOS memory cell which includes a floating gate charged from the substrate by avalanche injection. Charge is removed from the floating gate to an erasing gate by tunneling. Sharp edges on the polycrystalline silicon floating gate provide an enhanced electric field to overcome the silicon/silicon oxide barrier, thus permitting charge to be transferred from the floating gate to the erasing gate.
REFERENCES:
patent: 3755721 (1973-08-01), Frohman-Bentchkowsky
patent: 3825945 (1974-07-01), Masuoka
patent: 3996657 (1976-12-01), Simko
1972 Wescon Tech. Papers -- vol. 16, pp. 2-8.
Intel Corporation
Wojciechowicz Edward J.
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