Robust multiple word instruction and method therefor

Details Robust multiple word instruction and method therefor Robust multiple word instruction and method therefor

1997-09-29

1999-05-18

Eng, David Y.

G06F9/32

Patent

active

059058803

ABSTRACT:
An instruction set for a microcontroller which has robust multiple word instructions. The instruction set has a plurality of instructions wherein the plurality of instructions comprises single word instructions and multiple word instructions. At least one bit is located in a predetermined location in all non-first words of all multiple word instructions. The bit will be decoded by the microcontroller as no operation bit if the first word of the multiple word instruction is not executed prior to execution of any succeeding words in the multiple word instruction.

REFERENCES:
patent: 4566063 (1986-01-01), Zolnowsky et al.
patent: 4709324 (1987-11-01), Kloker
patent: 4872109 (1989-10-01), Horst et al.
patent: 5388233 (1995-02-01), Hays et al.
patent: 5732234 (1998-03-01), Vassilladis et al.
patent: 5758116 (1998-05-01), Lee et al.

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