Processor scheduling method for iterative loops

Details Processor scheduling method for iterative loops Processor scheduling method for iterative loops

1991-02-05

1993-07-20

Heckler, Thomas M.

Boots, shoes, and leggings

364DIG1, 3642805, G06F 906

Patent

active

052300536

ABSTRACT:
A compiling method is described whereby a source program written in a conventional high-language for execution by a serial architecture computer can be automatically converted to an object program for parallel execution by a multi-processor computer, without intervention by a programmer. Single loops or nested loops in source program are detected, and where possible are coded for concurrent execution of the outermost loop, with loop interchange in a nested loop, or fission of a loop into a plurality of adjacent loops being performed if necessary to enable concurrentization.

REFERENCES:
patent: 4686623 (1987-08-01), Wallace
patent: 4807126 (1989-02-01), Gotou et al.
patent: 4833606 (1989-05-01), Iwasawa et al.
patent: 5109331 (1992-04-01), Ishida et al.
patent: 5267068 (1992-11-01), Iwasawa et al.
"Advanced Compiler Optimizations for Supercomputers" by David A. Padua et al.; Communications of the ACM; Dec. 1986 vol. 29 No. 12.

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