Multiple address space system including address translator for r

Details Multiple address space system including address translator for r Multiple address space system including address translator for r

1992-04-07

1993-07-20

Lee, Thomas C.

Boots, shoes, and leggings

395400, 3642563, 3642564, 3642565, 364DIG1, 3649354, 3649614, G06F 1210, G06F 1208, G06F 1200

Patent

active

052300455

ABSTRACT:
Virtual addresses from multiple address spaces are translated to real addresses in main memory by generating for each virtual address an address space identifier (AID) identifying its address space. Then, the virtual address and its AID are used to obtain the real address. The address spaces include a shared address space, from which the processor can provide a virtual address at any time, as well as switched address spaces, from one of which the processor can provide a virtual address at a given time. If the processor's local cache does not have data for the virtual address and cannot translate the virtual address to a real address, the local cache provides the virtual address on a bus. A dedicated VLSI map cache is connected for receiving virtual addresses from the bus and for providing real addresses on the bus. The bus is also connected for providing real addresses to access memory. The map cache, which can handle address translation for multiple processors connected to the bus, translates by keeping the most recently accessed mapping entries, each of which associates a virtual address and its AID with a real address. If the virtual address is from the shared address space, the map cache uses the shared AID, but if not, the map cache uses the current switched AID for the processor providing the virtual address.

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