Method of and apparatus for assigning logic gates to a plurality

Details Method of and apparatus for assigning logic gates to a plurality Method of and apparatus for assigning logic gates to a plurality

1990-10-12

1993-07-20

Trans, Vincent N.

Boots, shoes, and leggings

364489, 364488, G06F 1560

Patent

active

052299538

ABSTRACT:
The logic gates are usually logically arranged in a first hierarchical structure in terms of a cluster of logical functions certain logic function elements are selected as to-be-processed function elements on the basis of the number of hardware components and a maximum allowable number of gates each hardware component can accommodate. Selected to-be-processed function elements in the first hierarchical structure are classified into at least two element groups based on connection strengths among the to-be-processed function elements and a maximum allowable number of pins and gates each hardware component can carry and accommodate, respectively. Using the classification result, the selected to-be-processed function elements in the first hierarchical structure are rearranged into a second hierarchical structure in terms of a cluster of logical functions in which all of the to-be-processed function elements are partitioned into the plurality of group elements so that each of the group elements corresponds to those of the logic function elements which are physically assignable to a different one of the hardware components.

REFERENCES:
patent: T940008 (1975-11-01), Oden et al.
patent: T943001 (1976-02-01), Mennone
patent: T944001 (1976-03-01), Hanan et al.
patent: 4636966 (1987-01-01), Yamada et al.
patent: 4815003 (1989-03-01), Putatunda et al.
patent: 4908772 (1990-03-01), Chi
"Partitioning and Placement Technique for CMOS Gate Arrays" by Odawara et al., IEEE Trans. on Computer-Aided Design, CAD-6, No. 3, May 1987, pp. 355-363.
"An Efficient Heuristic Procedure for Partitioning Graphs" by Kernighan et al., Bell System Tech. Journal, Feb. 1970, pp. 291-307.
"A Linear-Time Heuristic for Improving Network Partitions" by Fiduccia et al., IEEE 19th Design Automation Conf., 1982, pp. 175-179.
"Chortle: A Technology Mapping Program for Lookup Table-Based Field Programmable Gate Arrays" by Francis et al., 27th ACM/IEEE Design Automation Conf., 1990, pp. 613-619.

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