Timing control for PRML class IV sampling data detection channel

Details Timing control for PRML class IV sampling data detection channel Timing control for PRML class IV sampling data detection channel

1992-08-27

1993-11-02

Mai, Tan V.

Boots, shoes, and leggings

36472401, G06J 100, G06F 1531

Patent

active

052589331

ABSTRACT:
A multi-mode timing loop for a PR4,ML sampled data channel includes an analog to digital converter and a digital finite impulse response filter for providing conditioned digital samples. The timing loop includes a reference clock source for putting out a reference clock frequency related to a nominal sample data rate, a frequency controllable oscillator connected to generate a sample clock, an analog timing loop and a digital timing loop. The analog timing loop provides phase lock during non-data read mode, and during data read mode the digital timing loop provides a vernier offset for fine adjustment of phase lock to a static setting then provided by the analog timing loop.

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patent: 4847871 (1989-07-01), Matsushita et al.
patent: 4890299 (1989-12-01), Dolivo et al.
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