Method for fabricating metallization patterns on an electronic s

Details Method for fabricating metallization patterns on an electronic s Method for fabricating metallization patterns on an electronic s

1995-08-21

1997-01-07

Gorgos, Kathryn

Etching a substrate: processes

Forming or treating electrical conductor article

427124, 4271263, 427259, 427109, 20419232, 205122, 205221, 205222, 205223, 1566521, 216 23, 216 95, 216102, 216105, 359 88, 359 87, 437228, 437245, 437246, 437181, B05D 512, C23C 1400, C25D 502, H01L 21465

Patent

active

055914802

ABSTRACT:
One method for fabricating solderable pads (406) onto a substrate (220) for direct chip attachment uses a multilayer metallization coating (500). The coating has a bottom layer (202) of indium-tin oxide, with an intermediate layer (204) of copper and a top layer (206) of indium-tin oxide. A masking layer (208) is deposited on the active display area (402) of the substrate, leaving the bonding pads uncovered. The revealed bonding pads are then plasma etched, using the polyimide as an etch resist, and the top layer of ITO is selectively removed to reveal the underlying copper layer. The exposed copper layer (204) is then plated with a solderable metal to the desired thickness to form bonding pads that may be used with direct chip attachment schemes.

REFERENCES:
patent: 4358748 (1982-11-01), Gruner et al.
patent: 4495026 (1985-01-01), Herberg
patent: 4684436 (1987-08-01), Burns et al.
patent: 4917466 (1990-04-01), Nakamura et al.
patent: 4925524 (1990-05-01), Beatty

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