Method in a parallel test apparatus for semiconductor memories

Details Method in a parallel test apparatus for semiconductor memories Method in a parallel test apparatus for semiconductor memories

1990-05-25

1993-06-29

Beausoliel, Jr., Robert W.

Excavating

371 211, 371 70, G06F 1110

Patent

active

052241076

ABSTRACT:
A method in a parallel test apparatus provides for parallel testing a plurality of memory cells of a semiconductor module in parallel. The information read from the memory cells that are forwarded via the parallel test apparatus are tested to determine whether or not all cells are free of error. When exactly one error is present, the parallel test indicates the address of the faulty memory cell. Code words in the sense of the Hamming code are employed as test patterns. The length of the code words corresponds to the plurality of memory cells to be tested in parallel. The parallel test apparatus is constructed on the memory chip in the form of weighted parity check circuits.

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