Static information storage and retrieval – Powering
Patent
1990-04-16
1991-10-01
Fears, Terrell W.
Static information storage and retrieval
Powering
365227, 307450, G11C 1300
Patent
active
050540017
DESCRIPTION:
BRIEF SUMMARY
SUMMARY OF THE DISCLOSURE
In memory systems such as EEPROM or NVRAM, to transfer program and/or data a high voltage is required to write to or erase the memory cells and therefore, to avoid voltage breakdown in the buffer transistors of the memory cells at high voltages, protecting transistors are provided in connection with the buffer gates. The protecting transistors are only useful during the write/erase operation and at all other times the voltage applied to the protecting transistors' gates are selected so that the protecting transistors are switched "on" so as not to disturb the logic function of the memory system.
Such an arrangement is used in the MC68HC11 EEPROM write amplifier supplied by Motorola Inc. which is also designed so that it can operate with a three state function output. The tristate function is realised by a transmission gate able to support high voltage and which is coupled to the buffer gates. The transmission gate is made up of four coupled transistors. Since the buffer and transmission gate are connected to each column of the EEPROM memory a large number of transistors are required to create a tristate function resulting in greater circuit size and cost.
A similar arrangement of buffer gates and protecting transistors is found in the RAM cells of Non-Volatile RAM (NVRAM) memory systems such as that described in Applicant's UK patent application (No. 8702785) entitled "Memory System", the disclosure of which is hereby incorporated herein by reference. As with the above described write amplifier, in the memory system a high voltage for write/erase operation is required However it is also important to perform a full preset of the entire RAM array before performing a recall. This can be achieved by individually pulling down each cell using a respective transistor, however this requires a large number of transistors. The above referred to UK application discloses presetting the memory cells by using a single pull-down transistor per column. However, a very large transistor is required to pull-down all the RAM cells on the same column which can create significant power consumption and can make the preset difficult.
It is an object of the present invention to provide a high voltage transistor breakdown protection circuit for a memory system wherein the above disadvantages may be obviated.
In accordance with the present invention there is provided a high voltage transistor breakdown protection circuit comprising:
protecting means having a first and a second input;
protection control means coupled to said first and second inputs of said protecting means to apply first and second signals thereto,
said protecting means assuming a protecting or a non-protecting mode in dependence on said protection control means applying to said first and second inputs first and second combinations of said first and second signals, characterised by,
said protecting means being arranged to assume a third mode and a fourth mode in dependence on said protection control means applying to said first and second inputs third and fourth combinations of said first and second signals.
Thus, it will be appreciated that by replacing the transmission gate and the high voltage translator of the write amplifier by a circuit wherein the protection transistors are used both as protection against breakdown in the buffer transistors at high voltages and for creating the tristate function at low voltages, the number of transistors are reduced considerably, which reduces the circuit size and cost. Thus power consumption will be decreased and working safety improved.
It will also be appreciated that by using such a protecting circuit arrangement in the RAM cell of a NVRAM memory system a tristate effect can be created into the RAM cell thereby making the preset easier since the pull-up action of the p transistors in the memory cell during preset activation can now be disabled. Thus a large transistor is not required thereby reducing the power consumption.
Two memory systems in accordance with the present invention will now be de
REFERENCES:
patent: 4337525 (1982-06-01), Akatsuka
patent: 4384220 (1983-05-01), Segawa et al.
patent: 4385369 (1983-05-01), Sheppard
Bingham Michael D.
Botsch Bradley J.
Fears Terrell W.
Motorola Inc.
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