Fishing – trapping – and vermin destroying
Patent
1992-05-26
1993-07-20
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437913, 437235, 148DIG150, H01L 21265
Patent
active
052293106
ABSTRACT:
A thin-film transistor in a semiconductor device is self-aligned and vertically oriented. In one form of the present invention, the semiconductor device (10) has a vertical wall trench (18) formed in a first dielectric layer (16) and having a predetermined depth. A first current electrode (26) is formed on a bottom surface of the trench while a second current electrode (28) overlies the first dielectric material, each current electrode preferably being formed of polysilicon. A channel region (30) connecting the first and second current electrodes lies along the vertical wall of the trench and has a length substantially equal to the predetermined depth. A control electrode (36) is located within the trench and is also preferably formed of polysilicon. The control electrode is electrically isolated from the first current electrode and the channel region by a second dielectric layer (32).
REFERENCES:
patent: 4364074 (1982-12-01), Garnache et al.
patent: 4845537 (1989-07-01), Nishimura et al.
patent: 4845539 (1989-07-01), Inoue
patent: 4864374 (1989-09-01), Banerjee
patent: 4982250 (1991-01-01), Manos, II et al.
patent: 5012308 (1991-04-01), Hieda
patent: 5122848 (1992-06-01), Lee et al.
Goddard Patricia S.
Hearn Brian E.
Motorola Inc.
Trinh Michael
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