Output circuit for outputting a level shifted output signal

Details Output circuit for outputting a level shifted output signal Output circuit for outputting a level shifted output signal

1989-06-07

1990-02-27

Wong, Peter S.

Electricity: power supply or regulation systems

External or operator controlled

Using a three or more terminal semiconductive device as the...

323314, 307264, 307475, H03K 513

Patent

active

049049240

ABSTRACT:
An output circuit provides a high voltage output signal in response to a low voltage input signal. The output circuit includes a pull-up transistor for raising the output signal substantially to a power source voltage level and a pull-down transistor responsive to the input signal for lowering the output signal substantially to the ground level. The pull-up transistor is biased by a self-bias circuit triggered by a prescribed level of a control signal. The self-bias circuit continues to bias the pull-up MOS transistor in order to bring the output signal level to the high voltage level, even if the prescribed level period of the control signal terminates.

REFERENCES:
patent: 4565960 (1986-01-01), Takata et al.
patent: 4656374 (1987-04-01), Rapp
patent: 4694201 (1987-09-01), Jason
patent: 4695750 (1987-09-01), Hara et al.
patent: 4707623 (1987-11-01), Bismarck
patent: 4713600 (1987-12-01), Tsugaru et al.
patent: 4779016 (1988-10-01), Sugiyama et al.

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