Excavating
Patent
1990-02-01
1992-06-16
Beausoliel, Robert W.
Excavating
371 211, 365200, G06F 1120
Patent
active
051230160
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
Field of the Invention
The invention is directed to an arrangement and to a method for identifying and localizing faulty circuits of a memory module, particularly faulty memory cells, based on a self testing method.
Both as individual elements of a computer system as well as memory modules on LSI modules, memories assume an important role. Their development is advancing worldwide with wide spread application. Currently available memories have capacities up to a megabit. The trend is toward memory modules having an even higher capacity.
At present, memories are tested with the assistance of automatic test units. These can usually test only one module at a time. Whereas the manufacturing essentially dependent on the chip surface, the testing outlay increases with the number of elements to be tested per module. The share of testing costs in module costs is therefore increasing. The introduction of self-test methods allows one to expect an improvement in this situation. Some functions of the automatic test unit are thereby shifted into the module under test with additional circuits. It is not only static, but also some dynamic faults that can be recognized with what is referred to as on-chip testing. The self-test can sequence in parallel for all modules of a wafer or, respectively, for a plurality of modules. It is also possible to likewise utilize the self-test of the modules for a later assembly or, respectively, system test.
It is also known to repair faulty memory cells of a memory with the assistance of auxiliary rows of memory cells or auxiliary columns of memory cells. In order to be able to implement such a repair, the addresses of the faulty memory cells must be identified and retained. This ensues with the assistance of the automatic test unit that supplies the memory module with test patterns and that checks the resulting signals output by the memory module in response thereto. The evaluation of the resulting signals snows whether faulty memory cells are present. The addresses of faulty memory cells are then stored in the automatic test unit. A repair strategy is then prepared after the conclusion of the test, this indicating how the rows or columns having faulty memory cells must be replaced by replacement rows or, respectively, replacement columns. The selected replacement rows or replacement columns are activated by reprogramming and the rows or columns having faulty memory cells are disconnected. For example, fuses that can be activated with the assistance of laser light are employed for the reprogramming. Such methods are known, for example, from JST News, Vol. 3, No. 2, April 1984, Pages 18-26; IEEE Journal of Solid State Circuits, Vol. SC-18, No. 5, October 1983, pages 562-567; IEEE Journal of Solid State Circuits, Vol. SC-16, No. 5, October 1981, Pages 506-513; IEEE Design and Test, Vol. 6, Pages 35-44, 1985; Electronics, Jan. 12, 1984, Pages 175-179.
Memory self-test methods that are previously known do not support the above-recited repair possibilities. The self-test methods only supply a statement as to whether the memory module is faulty or is not faulty. In addition to a fault-free recognition, however, the self-test of reparable memory modules additionally requires that the faulty memory cells be localized and that a corresponding fault list be produced.
SUMMARY OF THE INVENTION
The object of the invention is comprised in specifying an arrangement and a method for identifying and localizing faulty circuits, particularly faulty memory cells, of a memory module, this working according to a self testing method of the memory module. A self-test of every memory module can be implemented With the assistance of this arrangement and the methods thereof and, moreover, a repair strategy can be produced on the basis of identified, faulty memory cells. The advantages of the self-test method in memory modules and the advantages of the repair possibility of high-capacity memory modules are thus achieved.
In an arrangement of the species initially cited, this objec
REFERENCES:
patent: 3995261 (1976-11-01), Goldberg
patent: 4191996 (1980-03-01), Chesley
patent: 4460999 (1984-07-01), Schmidt
patent: 4627053 (1986-12-01), Yamaki
patent: 4701920 (1987-10-01), Resnick
patent: 4736373 (1988-04-01), Schmidt
patent: 4745582 (1988-05-01), Fukushi
patent: 4751656 (1988-06-01), Conti
patent: 4759020 (1988-07-01), Amundson
patent: 4860260 (1989-08-01), Saito
patent: 4937790 (1990-06-01), Sasaki
patent: 4980888 (1990-12-01), Bruce
Jaspanese Patent Abstract, vol. 4, No. 58 (E-163) [1203] Mar. 10, 1983 (11) 57-207347.
Muller Bruno
Ritter Hartmut
Beausoliel Robert W.
Siemens Aktiengesellschaft
LandOfFree
Arrangement and method for identifying and localizing faulty cir does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Arrangement and method for identifying and localizing faulty cir, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Arrangement and method for identifying and localizing faulty cir will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1759205