Semiconductor device having a gate electrode consisting of a plu

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357 233, 357 236, 357 41, 357 45, H01C 2968, H01C 2910, H01C 2978, H01C 2702

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active

050538403

ABSTRACT:
Disclosed is a semiconductor device having a gate electrode consisting of a plurality of layers. The semiconductor device comprises a substrate, a first diffusion layer formed in the substrate, a second diffusion layer formed in the substrate, a floating gate electrode formed on a channel region between the first and second diffusion layers in an electrically floating state, and a control gate electrode formed on the floating gate electrode with an insulating film interposed therebetween. The first and second diffusion layers extend in parallel with each other along the longer side of the floating gate electrode. The control gate electrode extends in parallel with the shorter side of the floating gate electrode. The wiring layers for the first and second diffusion layers extend across the wiring layer for the control gate electrodes. Further, that portion of the first diffusion layer which is positioned adjacent to the floating gate electrode differs in impurity concentration from that portion of the second diffusion layer which is positioned adjacent to the floating gate electrode.

REFERENCES:
patent: 4377818 (1983-03-01), Kuo
patent: 4630085 (1986-12-01), Koyama
patent: 4763177 (1988-08-01), Paterson
IBM (Technical Disclosure Bulletin); "Selective oxidation of Titanium While Forming Titanium Silicide at Polysilicon and Diffusions"; 3/85; pp. 5870-5875.
Esquivel et al., "High Density Contractless, Self Aligned EPROM Cell Array Technology", IEDM Technical Digest, IEEE, pp. 592-595, Dec. 7, 1986.
International Electron Devices Meeting, Dec. 11-14, 1988, San Francisco, pp. 432-435, K. Yoshikawa et al, "An Asymmetrical Lightly-Doped Source (ALDS) Cell For Virtual Ground High Density EPROMS".

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