Power reduction design for ECL outputs that is independent of ra

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307455, 307467, 3072966, H03K 19086, H03K 19082

Patent

active

051226863

ABSTRACT:
A low voltage current mirror termination circuit used with an ECL gate array for providing a constant output emitter follower reference current (Ief) which is independent of voltage variations in a separate output emitter follower power supply source (VEF) includes a lateral PNP transistor (Qp), an NPN mirror transistor (Qx), at least one pull-down transistor (Qf), and at least one NPN output emitter follower transistor (Qo). The current through the collector of the lateral PNP transistor (Qp) defines a mirror current (Ip). The base of the lateral transistor (Qp) is connected to receive a base bias voltage VEP. The current through the collector of the pull-down transistor (Qf) defines the constant output emitter follower reference current (Ief) which is proportional to the mirror current (Ip). The separate emitter follower power supply source (VEF) has a voltage which is lower than a supply source (VEE) so as to reduce significantly the power consumption.

REFERENCES:
patent: 4638239 (1987-01-01), Hachimori
patent: 4804861 (1989-02-01), Hollstein et al.
patent: 4812734 (1989-03-01), Kohseik
patent: 5039884 (1991-08-01), Hara

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