Method and circuit configuration for suppressing short-time inte

Excavating

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371 9, 364187, 36442602, 36442603, 303 92, G06F 1120, B60T 888

Patent

active

047730722

ABSTRACT:
A method and a circuit configuration for suppressing sporadic interferences in the processing of data by means of two circuit systems (2, 3, MC1, MC2). The circuit systems redundantly process the data and, for the purpose of detecting errors and interferences, between the circuit systems data (D1n, D2n) is exchanged and compared for agreement. If the comparators (15, 16, 25', 41.2, 43.1, 46.2, 49.1) detect differences the transferred data will be taken over and the data processing will be continued with the transferred data. This takes place in several consecutive cycles. As soon as the predetermined scope or a predetermined number of cycles with differences between the compared data is exceeded an error will be evaluated and indicated. The circuit configuration is suitable for increasing the tolerance of electronic control circuits (ER) of the type for slip-controlled brake systems.

REFERENCES:
patent: 3618015 (1971-11-01), Homonick
patent: 4113321 (1978-09-01), Bleckmann
patent: 4198678 (1980-04-01), Maatje
patent: 4358823 (1982-11-01), McDonald
patent: 4493210 (1985-01-01), Fries
patent: 4546437 (1985-10-01), Bleckmann
patent: 4566101 (1986-01-01), Skonieczny

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