Process for forming a field isolation structure and gate structu

Details Process for forming a field isolation structure and gate structu Process for forming a field isolation structure and gate structu

1990-10-12

1992-06-16

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 67, 437 70, 357 2311, 357 47, H01L 21265

Patent

active

051224739

ABSTRACT:
Through a process perfectly suitable for fabricating integrated MISFET devices with an extremely high packing density, the field isolation structure and the gate structures of MISFET devices are simultaneously formed while attending an excellent planarity of the front of the wafer without the need of particularly burdensome techniques in order to preserve the crystallographic integrity of the substrate which is often negatively affected through conventional nitride process or by the etching of the silicon substrate as in BOX isolation processes. A patterned matrix layer of polycrystalline silicon is used for masking the active areas from the isolation implantation and from a subsequent low pressure chemical vapor deposition of a TEOS layer having a thickness substantially equal to the thickness of the masking matrix layer of polycrystalline silicon to form the field isolation structure. After having planarized the surface and exposed completely the top surfaces of the masking portions of the polycrystalline silicon matrix layer, a second layer of polycrystalline silicon is deposited and thereafter the polycrystalline silicon is doped. Finally the doped polycrystalline silicon is patterned by masking and etching steps for defining the gate structures.

REFERENCES:
patent: 4455740 (1934-06-01), Iwai
patent: 4506434 (1985-03-01), Ogawa et al.
patent: 4543706 (1985-10-01), Bencuya et al.
patent: 4697071 (1986-06-01), Kita
patent: 4829019 (1989-05-01), Mitchell et al.
patent: 4876216 (1989-10-01), Tobias et al.

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