Semiconductor memory device with shift during write capability

Details Semiconductor memory device with shift during write capability Semiconductor memory device with shift during write capability

1985-10-16

1988-09-20

Hecker, Stuart N.

Static information storage and retrieval

Plural shift register memory devices

365219, 365220, G11C 1900, G11C 1928

Patent

active

047730455

ABSTRACT:
A semiconductor memory device including a RAM portion and a shift register for enabling parallel transfer of a one word line amount of data of the RAM portion between the RAM portion and the shift register. The shift register is divided into a plurality of shift register portions with serial input data being distributed alternately between the shift register portions by the operation of a multiplexer and serial output data being obtained by picking up data alternately from the shift register portions by the operation of another multiplexer. A transfer gate portion is inserted between the RAM portion and the shift register for carrying out parallel transfer, the transfer gate portion includes a plurality of groups of transfer gates for enabling selective connections of input and output terminals of each of the stages of the shift register portions with either of the adjacent odd numbered bit line and even numbered bit line of the RAM portion. The plurality of transfer gate groups are switched in correspondence with shift clock signals.

REFERENCES:
patent: 4151609 (1979-04-01), Moss
patent: 4281401 (1981-07-01), Redwine et al.
patent: 4321695 (1982-03-01), Redwine et al.
patent: 4330852 (1982-05-01), Redwine
patent: 4347587 (1982-08-01), Rao
patent: 4616343 (1986-10-01), Ogawa
Patent Abstracts of Japan, vol. 1, No. 50, May 16, 1977, p. 3343, JP-A-51 147 225.

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