Method of forming doped polycrystalline silicon pattern by selec

Details Method of forming doped polycrystalline silicon pattern by selec Method of forming doped polycrystalline silicon pattern by selec

1981-12-21

1984-03-27

Roy, Upendra

Metal working

Method of mechanical manufacture

Assembling or joining

29571, 148 15, 148187, 156628, 156643, 156644, H01L 21302, H01L 21225, C23F 102

Patent

active

044385560

ABSTRACT:
A process of forming a polycrystalline silicon pattern which is used for a semiconductor device, wherein the degree of side etching is low and the obtained pattern is of high precision. Firstly, a polycrystalline silicon layer is deposited on a semiconductor substrate or on an insulating film which is formed on a semiconductor substrate. An impurity is selectively ion-implanted with high concentration into the region in the layer which is to remain as a polycrystalline silicon pattern. Finally, whole of the polycrystalline silicon layer into which the impurity is thus selectively ion-implanted is plasma-etched to etch off the areas into which the impurity is not ion-implanted.

REFERENCES:
patent: 3738880 (1973-06-01), Laker
patent: 3980507 (1976-09-01), Carley
patent: 4092209 (1978-05-01), Ipri
patent: 4093503 (1978-06-01), Harris
patent: 4209350 (1980-06-01), Ho et al.
Gotzlich et al., J. Electrochem. Soc. 128, (1981), 617.
Briska et al., IBM-TBB, 23 (1980), 199.

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