Boots – shoes – and leggings
Patent
1982-12-14
1986-07-15
Shaw, Gareth D.
Boots, shoes, and leggings
G06F 946, G06F 1516
Patent
active
046009922
ABSTRACT:
A data processing system including a dual ported main memory that can be accessed by I/O controllers via a common bus or directly by the central processing unit. The main memory is comprised of a volatile RAM array that requires periodic refreshing to prevent loss of information. Access to the main memory is controlled by a priority resolver that awards access to the main memory on the basis of predetermined priority levels assigned to CPU, I/O and refresh requests. The priority resolver produces an early signal that is usable to initiate a memory cycle before the final winner of the main memory is determined. The logic path of the lowest priority requester is the shortest path thus allowing the lowest priority requester to initiate a memory cycle in the shortest amount of time even though another requester may ultimately win use of the memory. The priority resolver also provides for the early resetting of access requests so that subsequent requests can be made with minimum delay.
REFERENCES:
patent: 4065809 (1977-12-01), Matsumoto
patent: 4128881 (1978-12-01), Yamamoto et al.
patent: 4334288 (1982-08-01), Booher
patent: 4415972 (1983-11-01), Adcock
Boudreau Daniel A.
Salas Edward R.
Dorsey Daniel K.
Grayson George
Honeywell Information Systems Inc.
Linnell William A.
Shaw Gareth D.
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