Read only memory with improved channel length control and method

Details Read only memory with improved channel length control and method Read only memory with improved channel length control and method

1988-06-10

1989-10-17

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 52, H01L 2996

Patent

active

048747157

ABSTRACT:
The specification discloses a floating gate read only memory formed in an array of rows (15) and columns (17) of memory cells (10). A conductivity-type determining layer (24) is formed over a face of a semiconductor body (30). An oxide layer (32) is formed over layer (24) and spaced apart elongated trenches (44) are formed through the layers (32) and (24) to form columns (17) of impurity layers. A first gate insulating layer (32a) is formed over the trenches (44). Discrete regions of polycrystalline silicon (34) are formed over spaced apart locations of the trenches (44) to form floating gates. A second gate insulating layer (36) is formed over the floating gates. A pattern of spaced apart parallel strips (40) are formed overlying the floating gates and normal to the columns (17) to form the rows (15) of memory cells.

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patent: 4502208 (1985-03-01), McPherson
patent: 4593454 (1986-06-01), Baudrant et al.

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