Method of making asymmetrically optimized CMOS field effect tran

Details Method of making asymmetrically optimized CMOS field effect tran Method of making asymmetrically optimized CMOS field effect tran

Filed on

1989-05-01

Date issued

1989-10-17

Examiner

Hearn, Brian E.

Patent Class

Fishing, trapping, and vermin destroying

Other Related Categories

437 41, 437 44, 437 56, 437 57, 437200, 437228, H01L 21265

Type

Patent

Status

active

Patent number

048747130

Description

ABSTRACT:
A process for forming an asymmetrically structured pair of CMOS field effect transistors having feature refinements matched to the individual idiosyncrasies of the p-channel and n-channel transistors. Complementary transistors are formed using a single photolithographic mask and a fabrication sequence which begins with the p-channel transistor source/drain formation. Thereafter, the p-channel transistor source/drain regions are metalized, the n-channel transistor lightly doped drain regions are formed, and the sidewall dielectric spaced n-channel transistor source/drain regions are formed using the p-channel metalization as a mask. The p-channel transistor source/drain metalization suppresses the effects of the relatively greater p-type source/drain resistivity, while the LDD structure of the n-channel transistor reduces performance degradation attributable to hot electron trapping. The structural asymmetry attributable to the process materially offsets performance limitations common to the individual CMOS transistor types.

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