Substrate for dielectric isolated integrated circuit with V-etch

Details Substrate for dielectric isolated integrated circuit with V-etch Substrate for dielectric isolated integrated circuit with V-etch

1975-05-19

1976-07-13

Larkins, William D.

357 55, 357 56, 357 60, H01L 2704, H01L 2712

Patent

active

039697495

ABSTRACT:
Process permitting control of the thickness of the thin layer of semiconductor material by first forming a slot of a predetermined depth in one surface so that the slot will be exposed during removal of material from the opposite surface should the thickness of the thin layer of semiconductor material become less than the depth of the slot, and a (110) oriented semiconductor substrate having a slot formed therein which is bounded by converging {111} planes.
In a preferred embodiment the thickness control is realized by first preparing the slice of semiconductor material so that at least one of its surfaces has a (100) orientation. There is then formed on the surface of the slice having the (100) orientation an etch-resistant mask having a window opened therethrough such that the window defines on the surface of the slice two lines which are parallel to each other and to lines defined by the intersection of {111} planes with the surface of the slice. Semiconductor material is then removed through the windows by etching to produce a slot having a depth greater than thickness to which the single crystal semiconductor material is to be subsequently processed. A vapor deposited support layer may then be produced on the surface of the slice to which the mask was attached during which process it will fill the slot etched in the semiconductor material through the window. Upon removal of the semiconductor material from the opposite surface of the slice, which may be affected by lapping and polishing, the support layer formed in the slot will become exposed, thus indicating that the thickness of the semiconductor material remaining is equal to or less than the depth of the slot etched in the first surface of the semiconductor material. At the time the first depth control slot is formed in the first surface of the semiconductor slice, there may also be performed a plurality of similar slots, the depth of which are controlled by controlling the width of the window in the etch resistant mask. Thus, as semiconductor material is removed from the slice, the thickness of the material remaining after the removal process can be determined by the number of slots exposed during lapping and polishing.

REFERENCES:
patent: 3411200 (1968-11-01), Formigoni
patent: 3419956 (1969-01-01), Kren et al.
patent: 3447235 (1969-06-01), Rosvold et al.
patent: 3454835 (1969-07-01), Rosvold
patent: 3489961 (1970-01-01), Frescura et al.
patent: 3509433 (1970-04-01), Schroeder
patent: 3766438 (1973-10-01), Castrucci et al.

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