Method of manufacturing lateral IGFETS including reduced surface

Details Method of manufacturing lateral IGFETS including reduced surface Method of manufacturing lateral IGFETS including reduced surface

1988-05-23

1990-02-27

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 45, 437 63, 437 59, 437917, H01L 21265

Patent

active

049046144

ABSTRACT:
A method of manufacturing a semiconductor device such as a lateral insulated gate field effect transistor is described in which impurities for forming first and second relatively shallow RESURF regions (8 and 11) of the opposite and the one conductivity type, respectively, are then introduced into the first region (4) and the semiconductor body is then heated first in an oxidizing atmosphere to cause the impurities to diffuse to form the RESURF regions (8 and 11) and to grow a relatively thick layer of insulating material on the given surface (3) at the same time. The relatively thick layer of insulating material is then defined to provide field oxide (14a) and gate oxide (14) then grown onto which is deposited a conductive gate layer (15,16) to form an insulated gate structure. Impurities are then introduced into the semiconductor body (3) using the insulated gate structure as a mask so as to form a lateral insulated gate field effect transistor (1).

REFERENCES:
patent: 4602266 (1986-07-01), Coe
patent: 4639761 (1987-01-01), Singer et al.
patent: 4774560 (1988-09-01), Coe
Glogolja, M., et al., "Smart-SIPMOS . . . ", Conference Record 1986 IEEE Industry Appl. Soc. Ann. Meet., part I, pp. 429-433.
Appels, J. A., et al., "Thin Layer High Voltage Devices," Philips J. Res., vol. 35, No. 1, 1980, pp. 1-13.

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