Patent
1984-06-28
1985-03-05
James, Andrew J.
357 13, 357 41, 357 91, H01L 2978, H01L 2990, H01L 2702, H01L 4900
Patent
active
045034486
ABSTRACT:
A semiconductor integrated device with a high tolerance against abnormally high input voltages comprises a first MIS transistor at the input stage and a second MIS transistor of the internal elements of the device. The source of the first MIS transistor is connected to an input electrode. The drain of the first MIS transistor is connected to the gate of the second MIS transistor. The source region of the first MIS transistor comprises phosphoric atoms. The other diffusion regions comprise arsenic atoms. Therefore, the depth of the source region of the first MIS transistor is greater than the other diffusion region. In addition, the source region of the first MIS transistor has a considerable gradient with regard to the concentration of the phosphoric atoms. As a result, the depletion layer between the source region of the first MIS transistor and the semiconductor substrate is broader than in the other region. Consequently, a high tolerance against abnormal high input voltages is obtained.
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Fujitsu Limited
Jackson Jerome
James Andrew J.
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