Power-down inverter circuit

Details Power-down inverter circuit Power-down inverter circuit

1983-08-31

1985-03-05

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307448, 307468, 307304, 365227, H03K 19003, H03K 19094

Patent

active

045033412

ABSTRACT:
A power-down inverter comprising three devices in series between supply voltage VDD and ground. A depletion load transistor connects the power supply rail to a first output node; a natural-threshold-voltage transistor, whose gate is controlled by the power-up signal, connects the first output node to a second output node, and an enhancement mode transistor, whose gate is controlled by the input signal to the inverter, connects the second output node to ground. This circuit provides an output (at the first output node) which is never floating, and it is therefore not necessary to use complementary signals for the power-up information. Moreover, the provision of two output nodes permits multiple output states to be available during the power-down mode if desired, depending on the full circuit configuration.

REFERENCES:
patent: 3775693 (1973-11-01), Proebsting
patent: 4384220 (1983-05-01), Segawa et al.
patent: 4408305 (1983-10-01), Kuo

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