Hard-wired serial Galois field decoder

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371 38, G06F 1110

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048336785

ABSTRACT:
An error detection and correction processor computes in real time successive approximations to a Galois field error locator polynomial and a Galois field error evaluator polynomial from the remainder or syndrome polynomial of a received block of data by executing successive iterations of a recursive algorithm. The processor stores each coefficient of the polynomials in an individually addressable memory location. During each iteration, the processor operates on successive ones of the coefficients of each polynomial in successive memory access cycles to compute a new version of the coefficient which replaces the old one in memory.

REFERENCES:
patent: 4633470 (1986-12-01), Welch et al.
IEEE Trans. on Computers, Shao, H. et al., "A VLSI Design of a Pipeline Reed-Solomon Decoder", vol. C-34, No. 5, May 1985, pp. 393-402.

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