Derived generation system for parity bits with bi-directional, c

Details Derived generation system for parity bits with bi-directional, c Derived generation system for parity bits with bi-directional, c

1996-01-26

1998-06-16

Elmore, Reba I.

Excavating

371 492, 371 501, G06F 1100

Patent

active

057682992

ABSTRACT:
A network in which an incoming word of 4 bytes and 4 parity bits is split into an address pointer and Tag address data into a Tag RAM storing two bytes which do not align with the incoming bytes and which leave a 2-bit (x,y,) crossed field. A programmable array logic Control PAL places correct parity values into a Parity RAM for the 2 stored bytes and later recreates the original word of 4 bytes and parity bits by using a flip-bit value (SPX) which simplifies the regeneration of correct parity values.

REFERENCES:
patent: 4761783 (1988-08-01), Christensen et al.
patent: 4852100 (1989-07-01), Christensen et al.
patent: 5555250 (1996-09-01), Walker et al.

Affiliated with

Also associated with

Rating

Derived generation system for parity bits with bi-directional, c does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Derived generation system for parity bits with bi-directional, c, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Derived generation system for parity bits with bi-directional, c will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1735064