Image processing system and phaselocked loop used therein

Details Image processing system and phaselocked loop used therein Image processing system and phaselocked loop used therein

1986-12-24

1989-05-23

Coles, Sr., Edward L.

Facsimile and static presentation processing

Facsimile

Recording apparatus

358280, 358283, H04N 1415

Patent

active

048335436

ABSTRACT:
The image processing system includes a fast packet switching network (PSNW) to which send an receive stations (SR, RC) are connected. Each image (AA) to be transmitted is subdivided into blocks by a grid (GR) which is displaceable with respect to the image and the groups of image signals corresponding to these blocks are encoded and transmitted to the network together with a signal (DX, DY), indicating the grid position, as a bitstream having a variable bitrate. The grid position is changed for each image transmission and in the receiver station use is made of a phaselocked loop (PLL) to derive a clock signal from reference signals of this bitstream.

REFERENCES:
patent: 4620233 (1986-10-01), Ogawa
patent: 4698689 (1987-10-01), Tzou
patent: 4754492 (1988-06-01), Macvar
patent: 4760460 (1988-07-01), Shimotohno

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