High density memory cell structure having a vertical trench tran

Details High density memory cell structure having a vertical trench tran High density memory cell structure having a vertical trench tran

1987-08-03

1989-05-23

James, Andrew J.

357 2312, 357 60, 357 55, H01L 2978, H01L 2904, H01L 2906

Patent

active

048335169

ABSTRACT:
A new high density vertical trench transistor and trench capacitor DRAM (dynamic-random-access memory) cell is described incorporating a wafer with a semiconductor substrate and an epitaxial layer thereon including a vertical transistor disposed in a shallow trench stacked above and self-aligned with a capacitor in a deep trench. The stacked vertical transistor 14 has a channel partly on the horizontal surface and partly along the shallow trench sidewalls. The drain of the access transistor is a lightly-doped drain structure connected to a bitline element. The source of the transistor, located at the bottom of the transistor trench and on top of the center of the trench capacitor, is self-aligned and connected to polysilicon contained inside the trench capacitor. Three sidewalls of the access transistor are surrounded by thick oxide isolation and the remaining one side is connected to drain and bitline contacts. The memory cell is located inside an n-well and uses the n-well and heavily-doped substrate as the capacitor counter-electrode plate. The cell storage node is the polysilicon inside the trench capacitor and include steps for growing epitaxial layers wherein an opening is left which serves as the shallow trench access transistor region and provides self-alignment with the deep trench storage capacitor.

REFERENCES:
patent: 3883948 (1975-05-01), Allison
patent: 4635090 (1987-01-01), Tamaki et al.
patent: 4645564 (1987-02-01), Morie et al.
patent: 4649625 (1987-03-01), Lu
IBM Technical Disclosure Bulletin, vol. 27, No. 12, May 1985, pp. 7051-7052, "Dynamic Ram Cell Structure".
IBM Technical Disclosure Bulletin, vol. 29, No. 5, Oct. 1986, "High Density Vertical Dram Cell", pp. 2335-2340.
IBM Technical Disclosure Bulletin, vol. 27, No. 11, Apr. 1985, "Dynamic Ram Cell with Merged Drain and Storage", pp. 6694-6699.

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