Method of simulating AC timing characteristics of integrated cir

Details Method of simulating AC timing characteristics of integrated cir Method of simulating AC timing characteristics of integrated cir

1996-05-02

1998-06-16

Teska, Kevin J.

Boots, shoes, and leggings

364490, 371 221, G06F 9455, G06F 1750

Patent

active

057681597

ABSTRACT:
A method of simulating AC timing characteristics at the pins of a device in of an application specific integrated circuit (ASIC) design is presented. The approach is fully automatic and is generalized, in the sense that both positive and negative Setup and Hold times and Propagation delays can be captured. The approach allows each bit of a data bus to be treated individually so as to be able to identify the worst case Setup time, Hold time and Propagation delay. Measurement is carried out in parallel for all data inputs and outputs. The need for manual intervention is eliminated and considerably reduces simulation time. Delay files are used through a call from a test bench, and the same testbench can be run on different delay information, namely pre-layout or post-layout delays.

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