Method of calculating macrocell power and delay values

Details Method of calculating macrocell power and delay values Method of calculating macrocell power and delay values

1995-05-15

1998-06-16

Teska, Kevin J.

Boots, shoes, and leggings

364554, 364579, 364578, G06F 1750

Patent

active

057681309

ABSTRACT:
Techniques for computing power and delay values for macrocells in an ASIC design are described whereby the power or delay values are encoded as a multi-dimensional mathematical expression relating the power or delay value to the values of a plurality of operating conditions. The mathematical expression is derived from a multiple regression analysis of a plurality of power or delay sample values determined for a plurality of specific operating conditions. Delay values are derived directly from the mathematical relationship. Power dissipation values are determined by encoding current draw as a function of the various operating conditions. When a predicted current draw value is computed, it is multiplied by a value of power supply voltage to determine power dissipation.

REFERENCES:
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patent: 5406497 (1995-04-01), Altheimer
patent: 5500808 (1996-03-01), Wang
patent: 5544071 (1996-08-01), Keren et al.
Lewis et al., "Smoothing Time Series for Input and Output Analysis In System Simulation Experiments", IEEE, 1990, pp. 46-48.
Elnaggar et al., "System Identification and Adaptive Control Based on a Variables Regression for Systems Having Unknown Delays," IEEE, 1990, pp. 1445-1450.
Vemuru et al., "A Model for Delay Evaluation of a CMOS Inverter", IEEE, 1990, pp. 89-92.

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