Set prediction cache memory system using bits of the main memory

Details Set prediction cache memory system using bits of the main memory Set prediction cache memory system using bits of the main memory

1992-10-05

1993-08-10

Anderson, Lawrence E.

Boots, shoes, and leggings

364DIG1, 36424345, G06F 1212, G06F 1210

Patent

active

052356973

ABSTRACT:
The set-prediction cache memory system comprises an extension of a set-associative cache memory system which operates in parallel to the set-associative structure to increase the overall speed of the cache memory while maintaining its performance. The set prediction cache memory system includes a plurality of data RAMs and a plurality of tag RAMs to store data and data tags, respectively. Also included in the system are tag store comparators to compare the tag data contained in a specific tag RAM location with a second index comprising a predetermined second portion of a main memory address. The elements of the set prediction cache memory system which operate in parallel to the set-associative cache memory include: a set-prediction RAM which receives at least one third index comprising a predetermined third portion of the main memory address, and stores such third index to essentially predict the data cache RAM holding the data indexed by the third index; a data-select multiplexer which receives the prediction index and selects a data output from the data cache RAM indexed by the prediction index; and a mispredict logic device to determine if the set prediction RAM predicted the correct data cache RAM and if not, issue a mispredict signal which may comprise a write data signal, the write data signal containing information intended to correct the prediction index contained in the set prediction RAM.

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Chang, et al., The 14th Annual International Symposium on Computer Architecture, "Cache Design of a Sub-Micron CMOS System/370", Jun. 1987, pp. 208-213.

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