Method for designing a memory tile for use in a tiled memory

Details Method for designing a memory tile for use in a tiled memory Method for designing a memory tile for use in a tiled memory

1999-04-05

2000-11-28

Le, Vu A.

Static information storage and retrieval

Addressing

Plural blocks or banks

36518909, 365 63, G11C 700

Patent

active

061544132

ABSTRACT:
A plurality of memory tiles (22) are arranged to form a tiled memory array (12) in an integrated circuit device (400). In accordance with the present invention, each of the memory tiles (22) in the tiled memory array (12) has charge source circuitry (24) to provide the sufficient reference voltages for proper operation of the memory tile (22). In addition, each memory tile (22) may include local error detection and correction circuitry (36b). To facilitate reliable operation, each memory tile may also include redundant rows and/or columns, and appropriate redundancy control circuitry (32c', 32c").

REFERENCES:
patent: 5574697 (1996-11-01), Manning
patent: 5659519 (1997-08-01), Lee et al.

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