Synchronous/asynchronous I/O channel check and parity check dete

Details Synchronous/asynchronous I/O channel check and parity check dete Synchronous/asynchronous I/O channel check and parity check dete

1991-06-11

1993-08-10

Canney, Vincent P.

Excavating

371 295, G06F 1110

Patent

active

052356027

ABSTRACT:
An improved I/O channel check and parity check detector includes two similar detection paths each of which includes a check detector, a glitch reject circuit, and a read back register. A memory parity error causes a bit to be set in the read back register. An I/O channel check sets another bit in a read back register provided a memory parity error has not been signalled. If such signal occurs, the channel check is rejected. The read back bits are read through a port allowing the system to determine the source of error.

REFERENCES:
patent: 3727142 (1973-04-01), De Sipio
patent: 3790881 (1974-02-01), Smith
patent: 4530095 (1985-07-01), Ryan
patent: 4962501 (1990-10-01), Byers et al.
patent: 4984213 (1991-01-01), Abdoo
patent: 4991085 (1991-02-01), Pleva
patent: 5033050 (1991-07-01), Murai

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