Scannable system with addressable clock suppress elements

Details Scannable system with addressable clock suppress elements Scannable system with addressable clock suppress elements

1991-03-21

1993-08-10

Atkinson, Charles E.

Excavating

G01R 3128

Patent

active

052356000

ABSTRACT:
A mesh comprised of intersecting control lines and clock-passing elements is distributed across the substrate of an integrated circuit (IC) chip to control the distribution of clock pulses to clock-sensitive scan latches also provided on the IC chip. The mesh consumes a relatively small portion of the surface area over the substrate. Clock-insensitive scan latches drive the control lines to create a pattern of enabled and disabled clock-passing elements such that the dynamic performance of one or more subcircuits on the IC chip can be tested through an on-chip scan testing subsystem.

REFERENCES:
patent: 4554664 (1985-11-01), Schultz
patent: 5101153 (1992-03-01), Morong, III

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