Method and arrangement for dividing the frequency of an alternat

Details Method and arrangement for dividing the frequency of an alternat Method and arrangement for dividing the frequency of an alternat

1991-12-13

1993-08-10

Malzahn, David H.

Boots, shoes, and leggings

377 48, H03L 718

Patent

active

052355314

ABSTRACT:
In a synchronous data network such as a synchronous digital hierarchy, frequency generators in every network node must be followed up by synchronous signals having, for example, a frequency of 2.048 or 1.544 MHz, and which are derived from a common frequency normal. A divider having a non-whole-numbered division factor that can also be utilized elsewhere is lacking for this. Over and above this, the possibility of correcting conditioned frequency errors by positive/zero
egative pulse stuffing is also lacking. The former is enabled by an arrangement comprising a divider 23 that is periodically switched between two auxiliary division factors (m, n). The latter is allowed by an arrangement wherein the positive (PST) and negative (NST) pulse stuffing signals proceed partly directly and partly delayed to a decoder and, via this decoder, to an accumulator. Addresses generated by the latter cause a memory pair for forward x-values and y-values defined dependent on the pulse stuffing signals via a multiplexer to a further accumulator whose carry signal drives the divider for the purpose of frequency correction.

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patent: 5088057 (1992-02-01), Amrany et al.
SP8000 Series High Speed Dividers Integrated Circuit Handbook, Nov., 1981, Dr. Pirmin N. Foerg, pp. 140-143.
IEEE Journal of Solid-State Circuits, vol. 24, No. 2, Apr., 1989, "A 14-bit 80-kHz Sigma-Delta A/D Converter: Modeling, Design, and Performance Evaluation", by Steven R. Norsworthy et al., pp. 256-266.
Ubertragungstechnik, "Die neue synchrone digitale Hierarchie" ntz No. 41, 1988, Wolfgang Ehrlich et al., pp. 570-574.

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